Electrical fuse circuit

ABSTRACT

An electrical fuse circuit includes, in addition to an independent power supply switch circuit, a plurality of fuse bit cells, each including a fuse element one end of which is connected to an output of the power supply switch circuit, and a first MOS transistor connected to the other end of the fuse element, wherein a diode is connected between the ground potential and the power supply switch circuit as an ESD countermeasure. The gate oxide film thickness of transistors of the fuse bit cells is equal to that of a low-voltage logic-type transistor, not that of a high-voltage I/O-type transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrical fuse circuit used as anOTP (One-Time-Programmable) memory.

2. Description of the Background Art

Electrical fuse circuits have been realized in the art, where each fuseelement is programmed by passing or not passing a current through thefuse element so as to or not to break the fuse element, and suchelectrical fuse circuits have widely been used as program devices fortrimming high-frequency semiconductor devices. Specifically, aconventional electrical fuse circuit includes a polysilicon electricalfuse element, and a bipolar transistor for passing a current forbreaking the electrical fuse element, wherein the bipolar transistor isused to pass a large current of about 1 A (ampere) through theelectrical fuse element to thereby break the electrical fuse element.

Recently, in the field of semiconductor integrated circuits (LSIs), atechnique has been developed for forming a silicide layer on apolysilicon layer to thereby reduce the resistance of a gate electrode.An electrical fuse element has been developed in the art by using thistechnique, including a polysilicon layer and a silicide layer formed onthe polysilicon layer, wherein the electrical fuse element has a lowresistance when the silicide layer is unbroken and has a high resistancewhen the silicide layer is broken by a current flow therethrough (see,for example, U.S. Pat. No. 5,708,291).

With the electrical fuse element, the instantaneous current required forbreaking the silicide layer is about 10 to 30 mA (milliamperes) for the130 nm or 90 nm process generation.

In a case where such electrical fuse elements using silicide areemployed for a program device for trimming a high-frequencysemiconductor device, or the like, the number of electrical fuseelements to be provided on each chip is four to eight, and it istherefore possible to break all the electrical fuse elements at onceusing a conventional general-purpose tester.

Metal fuses have conventionally been used as fuse elements forredundancy in LSIs such as DRAMs and SRAMs. Such metal fuses may bereplaced by electrical fuse elements using silicide as described above.However, this has problems as follows.

First, the number of fuse elements to be provided on each chip for RAMredundancy is 500 to 1,000. Breaking as many as 1,000 electrical fuseelements at once requires an instantaneous current of about 10 to 30 A.However, it is difficult with a conventional general-purpose tester tohave a localized current flow of 10 to 30 A inside an LSI chip, and adedicated tester will be needed. For example, in a case where there are1,000 independent electrical fuse circuits and the electrical fuseelements are programmed one by one, there are required a large number ofcontrol terminals. Where there are four control terminals per circuit,for example, 4,000 control terminals are needed, and such a schemecannot be implemented on system LSIs.

In view of such problems, United States Patent Application PublicationNo. 2006/0158920 discloses an electrical fuse circuit as follows.

FIG. 15 is a circuit diagram showing a configuration of the conventionalelectrical fuse circuit. Referring to FIG. 15, the electrical fusecircuit includes a plurality (n) of electrical fuse bit cells 500, and aprogramming shift register block 100 having a plurality (n) of stages.Each of the electrical fuse bit cells 500 includes one electrical fuseelement 501. Where a program data signal FBmTi (i=1 to n) is at the highlevel (hereinafter referred to as the “H level”), the electrical fuseelement 501 is broken while a program enable signal PBmTi (i=1 to n)from the programming shift register block 100 is at the H level. Theprogramming shift register block 100 produces single-pulse programenable signals PBmTi (i=1 to n) that successively bring the first,second, . . . , stages to the H level, and outputs the produced signalsto the first to n^(th) stages of electrical fuse bit cells 500,respectively.

The conventional electrical fuse circuit will now be described ingreater detail. Referring to FIG. 15, the electrical fuse bit cell 500includes the electrical fuse element 501, an NMOS transistor 502, and a2-input AND circuit 503.

One end of the electrical fuse element 501 is connected to the powersupply VDDHE (about 3.3 V) and the other end thereof is connected to thedrain of the NMOS transistor 502. The NMOS transistor 502 is connectedin series with the electrical fuse element 501, and the source thereofis connected to the ground terminal. The AND circuit 503 receives theprogram data signal FBmTi (i=1 to n) and the program enable signal PBmTi(i=1 to n), and outputs a program signal INmTi (i=1 to n) to the gate ofthe NMOS transistor 502.

The programming shift register block 100 includes n stages of shiftregisters (PSR) 101. The n stages of shift registers 101 are connectedtogether in series, wherein each stage receives, as its input, theoutput from the preceding stage, with the first stage receiving aprogram control signal FPGI. A common program clock signal PCK is inputto all of the first to n^(th) stages of shift registers 101. The programenable signals PBmTi (i=1 to n) output from the n shift registers 101 inthe programming shift register block 100 are input to the first ton^(th) stages of electrical fuse bit cells 500, respectively.

FIG. 16 is a circuit diagram showing, in greater detail, theconfiguration of a single stage of shift register 101 in FIG. 15.Referring to FIG. 16, the shift register 101 includes two CMOStransmission gates 102 and 105, two inverter circuits 103 and 106, andtwo tri-state inverter circuits 104 and 107.

The first CMOS transmission gate 102 receives a program enabletransmission signal PAmT(i−1), which is an output from the (i−1)^(th)stage, with the program clock signal PCK being input to a gate of a PMOStransistor, and an inverted signal NCK derived from the program clocksignal PCK being input to a gate of an NMOS transistor. The programcontrol signal FPGI is input to the first CMOS transmission gate 102 ofthe first stage.

The first inverter circuit 103 receives an output of the first CMOStransmission gate 102. The first tri-state inverter circuit 104 receivesan output of the first inverter circuit 103, and uses the program clocksignal PCK as its control signal (means “enable” when at the H level) tothereby give an output to a node between the first CMOS transmissiongate 102 and the first inverter circuit 103.

The second CMOS transmission gate 105 receives an output of the firstinverter circuit 103, with the inverted signal NCK derived from theprogram clock signal PCK being input to a gate of a PMOS transistor, andthe program clock signal PCK being input to a gate of an NMOStransistor.

The second inverter circuit 106 receives an output of the second CMOStransmission gate 105 to output the program enable transmission signalPAmTi and the program enable signal PBmTi.

The second tri-state inverter circuit 107 receives an output of thesecond inverter circuit 106, and uses the inverted signal NCK derivedfrom the program clock signal PCK as its control signal (means “enable”when at the H level) to thereby give an output to a node between thesecond CMOS transmission gate 105 and the second inverter circuit 106.

FIG. 17 is a waveform diagram showing an operation of the electricalfuse circuit of FIG. 15. First, the operation of the electrical fuse bitcell 500 of the i^(th) stage will be described.

In a programming operation, first, the program data signal FBmTi inputto one input terminal of the AND circuit 503 is set to the H level or tothe low level (hereinafter referred to as the “L level”). Specifically,the program data signal FBmTi is set to the H level when the electricalfuse element 501 should be broken, and to the L level when theelectrical fuse element 501 should remain unbroken.

The program enable signal PBmTi is input to the other input terminal ofthe AND circuit 503. The electrical fuse bit cell 500 can break theelectrical fuse element 501 only while the program enable signal PBmTiis at the H level. Specifically, where the program data signal FBmTi isat the H level, while the program enable signal PBmTi is at the H level,the program signal INmTi being the output of the AND circuit 503 goes tothe H level to turn ON the NMOS transistor 502, thereby passing acurrent flow through the electrical fuse element 501, thus breaking theelectrical fuse element 501. Where the program data signal FBmTi is atthe L level, even if the program enable signal PBmTi goes to the Hlevel, the output INmTi of the AND circuit 503 remains at the L level,and the NMOS transistor 502 remains OFF, whereby no current flowsthrough the electrical fuse element 501, thus not breaking theelectrical fuse element 501 (i.e., it remains unbroken).

The overall operation of the electrical fuse circuit will now bedescribed. For example, in a case where the n electrical fuse bit cells500 are to be programmed to 1, 0, . . . , 1, the signal levels ofprogram data signals FBmT1, FBmT2, . . . , FBmTn are first set to H, L,. . . , H, respectively.

Then, the program control signal FPGI to be input to the first stage ofthe programming shift register block 100 is brought from the L level tothe H level while keeping a sufficient setup time with respect to therising edge of the program clock signal PCK. Since the program clocksignal PCK is at the L level, the first CMOS transmission gate 102 (seeFIG. 16) is ON, and the program control signal FPGI being at the H levelis input to the shift register 101 of the first stage while the programclock signal PCK is at the L level.

When the program clock signal PCK rises from the L level to the H level,the first CMOS transmission gate 102 is turned OFF, and the output (theL level) of the first inverter circuit 103 is latched by the firstinverter circuit 103 and the first tri-state inverter circuit 104 of thefirst stage and, at the same time, the second CMOS transmission gate 105is turned ON, whereby a program enable signal PBmT1 and a program enabletransmission signal PAmT1 of the first stage go to the H level. Theprogram control signal FPGI falls to the L level while the program clocksignal PCK is at the H level.

Then, when the program clock signal PCK falls from the H level to the Llevel, the first CMOS transmission gate 102 is again turned ON, wherebythe program control signal FPGI being at the L level is input to theshift register 101 of the first stage and, at the same time, the secondCMOS transmission gate 105 is turned OFF, and the output (the H level)of the second inverter circuit 106 is latched by the second invertercircuit 106 and the second tri-state inverter circuit 107 of the firststage, whereby the program enable signal PBmT1 and the program enabletransmission signal PAmT1 of the first stage are held at the H level.While the program clock signal PCK is at the L level, the program enabletransmission signal PAmT1 at the H level is input to the shift register101 of the second stage.

Such an operation of the programming shift register block 100successively produces the program enable signals PBmTi (i=1 to n) andthe program enable transmission signals PAmTi (i=1 to n), each having awidth equal to one cycle of the program clock signal PCK, as the programclock signal PCK periodically repeats its cycle.

When the program enable signal PBmTi input to the AND circuit 503 of theelectrical fuse bit cell 500 (i=1 to n) goes to the H level, theelectrical fuse bit cell 500 programs the electrical fuse element 501.Thus, the states of the program signals INmTi (i=1 to n) output from theAND circuits 503 are successively determined according to the programdata signals (FBmT1, FBmT2, . . . , FBmTn)=(H, L, . . . , H), each atthe rising edge of the program clock signal PCK.

In the example shown in FIG. 17, as the program enable signal PBmT1 ofthe first stage goes to the H level, the output INmT1 of the AND circuit503 of the electrical fuse bit cell 500 of the first stage goes to the Hlevel, and the NMOS transistor 502 is turned ON while a periodcorresponding to the pulse width of the program clock signal PCK tothereby break the electrical fuse element 501 of the first stage. Incontrast, even when a program enable signal PBmT2 of the second stagegoes to the H level, the output INmT2 of the AND circuit 503 of theelectrical fuse bit cell 500 of the second stage remains at the L level,and the NMOS transistor 502 remains OFF, whereby the electrical fuseelement 501 of the second stage is kept unbroken. Although not shown inthe figure, the electrical fuse elements 501 are kept unbroken in thethird to (n−1)^(th) stages, as in the second stage. As a program enablesignal PBmTn of the last stage goes to the H level, the electrical fuseelement 501 in the last stage is broken, as in the first stage.

As described above, the electrical fuse elements 501 are programmed oneby one by using the single-pulse program enable signals PBmTi (i=1 to n)from the programming shift register block 100. Thus, a programmingoperation can be performed using a conventional general-purpose tester.Moreover, with the plurality of shift registers 101 being connectedtogether in series, the total number of terminals can be reduced,thereby realizing an electrical fuse circuit that can be implemented ona system LSI.

With the conventional electrical fuse circuit, however, it is necessaryto apply a voltage of 2.4 V or more across an electrical fuse element inorder to pass a current of about 20 mA to break the electrical fuseelement where the resistance of the electrical fuse element is 120 ohms.Accordingly, a 3.3 V-I/O NMOS transistor is used to apply a voltage ofabout 3 V across the electrical fuse element. Therefore, theconventional electrical fuse circuit requires a large 3.3-V I/O-typeNMOS transistor whose gate width W is about 60 μm as a switch transistorfor producing a required current flow for breaking the electrical fuseelement. A 3.3-V I/O-type transistor is used also for the input to thegate of the NMOS transistor, and the area of the electrical fuse circuitis increased (the area of a 3.3-V I/O-type transistor is about twice aslarge as that of a 1.2-V logic-type transistor). If the production yieldof memory cells decreases as the process rule further shrinks in thefuture, the number of electrical fuse elements to be provided mayfurther increase, in which case the issue of the area of an electricalfuse circuit will be more serious.

In view of this, in a conventional electrical fuse circuit shown in FIG.15, a 1.2-V logic-type transistor may be used as the NMOS transistor.However, with the conventional electrical fuse circuit, the same voltage(about 3.3 V) as the voltage applied to the top of the electrical fuseelement is constantly applied also to the drain of the NMOS transistorwhile the gate voltage of the NMOS transistor is 0 V, hence a potentialdifference of about 3.3 V between the gate and the drain of the NMOStransistor, whereby the TDDB deterioration progresses.

On the other hand, the variety of applications of OTP memory deviceshave recently been extended. It is likely that OTP memory devices willin the future find applications such as, for example, system LSI chipshaving an ID function of storing system settings unique to each unit ora secure ID function of protecting information, semiconductor chipshaving a chip ID function of storing, for each chip, the lot number, thecoordinates of the position of the chip, the pre-shipping inspectionrecords, etc., so as to enable tracing (e.g., defect analysis), and ICtags used for tracking purposes such as logistics management andidentification of baggage of airplane passengers.

For these applications, a medium-sized OTP memory of about 1 to 10 Kbitsis used. Such an OTP memory is produced in large volumes, and should besufficiently inexpensive to produce so as not to affect the cost of theproduct or service in which it is used.

Where an OTP memory is provided on a system LSI of a state-of-the-artprocess, the OTP memory should be able to be designed in a logic-based,timely manner, as with an SRAM. A non-volatile memory such as a flashmemory requires an additional process, and the development thereof fallsbehind the state-of-the-art process by a few generations. In view of thetiming of marketing, the manufacturing cost, etc., such a memory cannotmeet demands in the market for systems using the state-of-the-artprocess, even though it is rewritable.

An electrical fuse circuit using silicide as described above may be usedas an OTP memory capable of meeting such demands in the market. Theelectrical fuse circuit, which is used by breaking a silicide layer on apolysilicon layer, does not require an additional process as does aflash memory, but can be designed in a logic-based manner. However, aconventional electrical fuse circuit with a configuration as describedabove has a significant impact in terms of the chip area it occupies,and significantly affects the manufacturing cost.

SUMMARY OF THE INVENTION

As described above, an I/O-type transistor having a large gate width isused in the prior art as a program driver for passing a current flowrequired for programming an electrical fuse element, thereby increasingthe area of the electrical fuse circuit.

It is therefore a first object of the present invention to realize anelectrical fuse circuit with which it is possible to reduce the totalarea.

Because of the principle of operation that an electrical fuse element isprogrammed by breaking the electrical fuse element by means of a currentflow therethrough, it is necessary for an electrical fuse circuit that acurrent is reliably prevented from flowing through the electrical fuseelement except when the electrical fuse element is programmed. In otherwords, it is important to ensure that the electrical fuse element can bebroken reliably when being programmed while it is reliably preventedfrom being broken otherwise. A cause for an erroneous breaking of anelectrical fuse element is an ESD surge current. Therefore, anelectrical fuse circuit needs to have countermeasures against theerroneous breaking of electrical fuse elements upon ESD application. Theprovision of an anti-ESD circuit will increase the total area of theelectrical fuse circuit. Therefore, it is important to provide theanti-ESD circuit with a small area.

It is therefore a second object of the present invention to provide acircuit for preventing an erroneous breaking of an electrical fuse so asto ensure the safety of an electrical fuse circuit, and to reduce thearea of such a circuit.

In order to achieve the first object set forth above, the presentinvention is directed to an electrical fuse circuit, in which a fuseelement is broken by a current flow therethrough, including a pluralityof fuse bit cells, each including, in addition to an independent powersupply switch circuit, a fuse element one end of which is connected toan output of the power supply switch circuit, and a first MOS transistorconnected to the other end of the fuse element, wherein a gate oxidefilm thickness of a transistor of the fuse bit cell is equal to that ofa logic transistor. Thus, it is possible to significantly reduce thearea of the electrical fuse circuit.

In order to achieve the second object set forth above, the presentinvention is directed to an electrical fuse circuit, in which a fuseelement is broken by a current flow therethrough, including a pluralityof fuse bit cells, each including, in addition to an independent powersupply switch circuit, a fuse element one end of which is connected toan output of the power supply switch circuit, and a first MOS transistorconnected to the other end of the fuse element, wherein a diode isconnected between a ground potential and the output of the power supplyswitch circuit, with an anode of the diode being connected to the groundpotential and a cathode of the diode being connected to the output ofthe power supply switch circuit. Thus, it is possible to prevent anelectrical fuse in an electrical fuse circuit from being brokenerroneously, while reducing the total area.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of an electricalfuse circuit according to an embodiment of the present invention.

FIG. 2 shows in detail a level shift circuit in the electrical fuse bitcell of FIG. 1.

FIG. 3 shows in detail a level shift circuit in the power supply switchcircuit of FIG. 1.

FIG. 4 is a waveform diagram showing an operation of the electrical fusecircuit of FIG. 1.

FIG. 5 is a circuit diagram showing a configuration of an electricalfuse circuit according to another embodiment of the present invention.

FIG. 6 is a waveform diagram showing an operation of the electrical fusecircuit of FIG. 5.

FIG. 7 is a plan view showing an example of a system LSI including theelectrical fuse circuit of FIG. 1 or 5.

FIG. 8 is a plan view showing another example of a system LSI includingthe electrical fuse circuit of FIG. 1 or 5.

FIG. 9 is a plan view showing the layout of a single I/O cell in asystem LSI.

FIG. 10 is a circuit diagram of FIG. 9, showing a single I/O cell.

FIG. 11 is a plan view showing still another example of a system LSIincluding the electrical fuse circuit of FIG. 1 or 5.

FIG. 12 is a cross-sectional view taken along line XII-XII of FIG. 11.

FIG. 13 is a plan view showing still another example of a system LSIincluding the electrical fuse circuit of FIG. 1 or 5.

FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 13.

FIG. 15 is a circuit diagram showing a configuration of the conventionalelectrical fuse circuit.

FIG. 16 is a circuit diagram showing, in greater detail, theconfiguration of a single stage of shift register in FIG. 15.

FIG. 17 is a waveform diagram showing an operation of the electricalfuse circuit of FIG. 15.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described withreference to the drawings. In a programming operation, an electricalfuse circuit programs each electrical fuse element by passing or notpassing a current through the electrical fuse element so as to or not tobreak the electrical fuse element. A power supply VDD25 (about 2.5 V) isherein assumed as the power supply for programming electrical fuseelements. Note that the power supply for programming electrical fuseelements is not limited to the power supply VDD25 (about 2.5 V), but maybe a power supply VDD33 (about 3.3 V).

FIG. 1 is a circuit diagram showing a configuration of an electricalfuse circuit according to an embodiment of the present invention.Referring to FIG. 1, the electrical fuse circuit of the presentinvention includes a plurality (n) of electrical fuse bit cells 200, aprogramming shift register block 100 having a plurality (n) of stages,and a power supply switch circuit 300. The programming shift registerblock 100 and the plurality of electrical fuse bit cells 200 togetherform an electrical fuse section 600. The programming shift registerblock 100 is as described above with reference to FIGS. 15 and 16, andwill not be further described below.

First, the electrical fuse bit cell 200 will be described. Referring toFIG. 1, the electrical fuse bit cell 200 includes an electrical fuseelement 201, a 1.2-V logic-type NMOS transistor 202 being a first MOStransistor, first and second AND circuits 203 and 205, and a level shiftcircuit (LS1) 204. The 1.2-V logic-type transistor 202 is not limited toa 1.2-V transistor, but the same effect will be achieved with any otherappropriate logic-type transistor such as a 1.0-V transistor.

The electrical fuse element 201 includes a polysilicon layer and asilicide layer formed on the polysilicon layer, wherein the electricalfuse element 201 has a low resistance when the silicide layer isunbroken and has a high resistance when the silicide layer is broken bya current flow therethrough. One end of the electrical fuse element 201is connected to the drain of the NMOS transistor 202. The NMOStransistor 202 is connected in series with the electrical fuse element201, and the source thereof is connected to the ground potential (VSS).The output signal line (VGB) of the power supply switch circuit 300 isconnected to the other end of the electrical fuse element 201.

The first AND circuit 203 is made of 1.2-V logic-type transistors, anduses a 1.2-V power supply (VDD) as its power supply. The 2-input ANDcircuit 203 receives the program data signal FBmTi (i=1 to n) and theprogram enable signal PBmTi (i=1 to n), and outputs a signal LS1mINi(i=1 to n) to the level shift circuit 204. The program data signal FBmTiis set to the H level (the VDD level) when breaking the electrical fuseelement 201, and to the L level when keeping the electrical fuse element201 unbroken. Therefore, when breaking the electrical fuse element 201,the output LS1mINi of the first AND circuit 203 goes to the H level (theVDD level) while the program enable signal PBmTi is at the H level (theVDD level). When not breaking the electrical fuse element 201, theoutput LS1mINi is at the L level, irrespective of the program enablesignal PBmTi.

The level shift circuit 204 receiving the output LS1mINi (i=1 to n) ofthe first AND circuit 203 uses the power supply VDD and the signal VGBas its power supplies to convert the VDD level to the voltage level ofthe signal VGB. The output LS1mOUTi (i=1 to n) of the level shiftcircuit 204 is at the voltage level of the signal VGB while the programenable signal PBmTi is at the H level when breaking the electrical fuseelement 201, and is at the L level when not breaking the electrical fuseelement 201.

The second AND circuit 205 is made of 2.5-V I/O-type transistors havinga thick gate oxide film, and uses the signal VGB as its power supply.The 2-input AND circuit 205 receives the output LS1mOUTi of the levelshift circuit 204 and a fuse program enable signal FPEN, and outputs theprogram signal INmTi (i=1 to n) to the gate of the NMOS transistor 202.

The fuse program enable signal FPEN is a control terminal signal,independent of the power supply VDD25 of the electrical fuse circuit,and is set to the VDD25 level in a programming operation and fixed tothe L level in a non-programming operation. The power supply VDD25(about 2.5 V) has a greater power supply voltage than the power supplyVDD (about 1.2 V). As will be described later, the signal VGBtransitions between the VDD level and the VDD25 level in synchronismwith the clock cycle of the program clock signal PCK. Therefore, whenbreaking the electrical fuse element 201, the program signal INmTitransitions to the VDD25 level while the program enable signal PBmTi isat the H level and the signal VGB is at the VDD25 level.

As described above, the electrical fuse bit cell 200 includes the levelshift circuit 204 for voltage conversion along the signal line thatconnects to the gate of the NMOS transistor 202. The level shift circuit204 performs a voltage conversion only when breaking the electrical fuseelement 201, to thereby produce the signal LS1mOUTi having the voltagelevel of the signal VGB. In a programming operation, the fuse programenable signal FPEN is set to the H level (the VDD25 level). Therefore,while the signal LS1mOUTi is at the VDD25 level (in a programmingoperation), the second AND circuit 205 produces a program signal INmTiat the VDD25 level and applies the produced signal to the gate of theNMOS transistor 202 to thereby turn ON the NMOS transistor 202. Thus, bysetting the gate voltage to the VDD25 level, it is possible even with a1.2-V logic-type NMOS transistor to pass a current necessary forbreaking the electrical fuse element 201 when the signal VGB applied tothe top of the electrical fuse element 201 is at the VDD25 level.

Next, the power supply switch circuit 300 will be described. The powersupply switch circuit 300 includes a 2.5-V I/O-type PMOS transistor 301that is connected in series with each electrical fuse element 201,whereby the signal VGB at the VDD25 level is applied from the PMOStransistor 301 commonly to the electrical fuse bit cells 200 each timethe program clock signal PCK rises from the L level to the H level. Aplurality of electrical fuse bit cells 200 are connected to the outputsignal VGB of the power supply switch circuit 300.

Referring to FIG. 1, the power supply switch circuit 300 includes the2.5-V I/O-type PMOS transistor 301, a 2.5-V I/O-type CMOS transmissiongate 302, inverter circuits 303 and 307, an AND circuit 304, a levelshift circuit (LS2) 305, and an NAND circuit 306.

The source of the PMOS transistor 301 is connected to the power supplyVDD25, the gate thereof receives a program enable switch signal PRGmIN,and the drain thereof is connected to the electrical fuse elements 201.One of the source and the drain of the CMOS transmission gate 302, whichis connected in parallel to the PMOS transistor 301, is connected to thepower supply VDD, the gate thereof receives the program enable switchsignal PRGmIN, and the other one of the source and the drain thereof isconnected to the electrical fuse elements 201. With the PMOS transistor301 and the CMOS transmission gate 302, either VDD25 or VDD canselectively be output from the output VGB of the power supply switchcircuit 300.

Thus, the program enable switch signal PRGmIN is commonly input to thePMOS transistor 301 and the CMOS transmission gate 302, and when thesignal PRGmIN goes to the H level (the VDD25 level), the PMOS transistor301 is turned OFF and the CMOS transmission gate 302 is turned ON,whereby the output signal VGB of the power supply switch circuit 300 isat the VDD level. When the program enable switch signal PRGmIN goes tothe L level, the PMOS transistor 301 is turned ON and the CMOStransmission gate 302 is turned OFF, whereby the output signal VGB ofthe power supply switch circuit 300 is at the VDD25 level. Therefore, avoltage of the VDD25 level is applied to the electrical fuse element 201of each electrical fuse bit cell 200 in a programming operation, and avoltage of the VDD level is applied to the electrical fuse element 201of each electrical fuse bit cell 200 in a non-programming operation.

Taking the design margin of the power supply VDD into consideration, itis possible to stably pass and output VDD by using the CMOS transmissiongate 302 as a transistor that is connected to the power supply VDD.Thus, it is possible to realize a stable output operation of the powersupply switch circuit 300.

The inverter circuit 303 receives a signal LAPAmTn. The signal LAPAmTnis produced by latching the falling edge of the program enabletransmission signal PAmTn, being the output of the last stage of theprogramming shift register block 100.

The AND circuit 304 is made of 1.2-V logic-type transistors, and usesVDD as its power supply. The 2-input AND circuit 304 receives an outputof the inverter circuit 303 and the program clock signal PCK, andoutputs a signal LS2mIN to the level shift circuit 305. The level shiftcircuit 305, receiving an output LS2mIN of the AND circuit 304, uses thepower supplies VDD and VDD25 as is power supplies to convert the VDDlevel to the VDD25 level.

The NAND circuit 306 is made of 2.5-V I/O-type transistors, and uses thepower supply VDD25 as its power supply. The 2-input NAND circuit 306receives an output LS2mOUT of the level shift circuit 305 and the fuseprogram enable signal FPEN to produce the program enable switch signalPRGmIN and output the produced signal commonly to the gates of the PMOStransistor 301 and the CMOS transmission gate 302.

With such a configuration, the program enable switch signal PRGmIN isproduced, which repeats its cycle in synchronism with the clock pulsesof the program clock signal PCK, inside the power supply switch circuit300. Specifically, the program enable switch signal PRGmIN transitionsto the L level and the output VGB of the power supply switch circuit 300is brought to the VDD25 level, each time the program clock signal PCKrises from the L level to the H level. Similarly, the program enableswitch signal PRGmIN transitions to the H level (the VDD25 level) andthe output VGB of the power supply switch circuit 300 is brought to theVDD level, each time the program clock signal PCK falls from the H levelto the L level.

Thus, in synchronism with the program clock signal PCK, the power supplyswitch circuit 300 alternately turns ON the PMOS transistor 301 and theCMOS transmission gate 302, whereby the output VGB transitions betweenthe VDD25 level and the VDD level.

On the other hand, as the program clock signal PCK periodically repeatsits cycle, the programming shift register block 100 successively outputsone-shot pulse signals each having a pulse width equal to one cycle ofthe program clock signal PCK (i.e., the program enable signals PBmTi(i=1 to n)) to the first to n^(th) stages of electrical fuse bit cells200, respectively.

Therefore, where the program data signal FBmTi is at the H level, theelectrical fuse bit cell 200 can apply the program signal INmTi at theVDD25 level to the gate of the NMOS transistor 202 to thereby break theelectrical fuse element 201 while the program enable signal PBmTi is atthe H level and the output signal VGB of the power supply switch circuit300 is at the VDD25 level.

FIG. 2 shows in detail the level shift circuit 204 in the electricalfuse bit cell 200 of FIG. 1. The level shift circuit 204 includes firstand second NMOS transistors 112 and 113, first and second PMOStransistors 114 and 115 each being a 1.2 V logic-type transistor, and aninverter circuit 116 made of 1.2 V logic-type transistors.

The gate of the first NMOS transistor 112 receives the output LS1mINi ofthe first AND circuit 203. The power supply of the inverter circuit 116is VDD. The drain of the second NMOS transistor 113 is the outputterminal LS1mOUTi of the level shift circuit 204.

The gate of the first PMOS transistor 114 is connected to the drain ofthe second NMOS transistor 113 (the output terminal LS1mOUTi of thelevel shift circuit), the drain thereof is connected to the drain of thefirst NMOS transistor 112, and the source thereof receives the outputsignal VGB of the power supply switch circuit 300. The gate of thesecond PMOS transistor 115 is connected to the drain of the first PMOStransistor 114, the drain thereof is connected to the drain of thesecond NMOS transistor 113 (the output terminal LS1mOUTi of the levelshift circuit), and the source thereof receives the output signal VGB ofthe power supply switch circuit 300.

With such a configuration, when the signal LS1mNi being the input signalof the level shift circuit 204 is at the L level, the first NMOStransistor 112 is OFF, the second NMOS transistor 113 is ON, the firstPMOS transistor 114 is ON and the second PMOS transistor 115 is OFF,whereby the signal level of the output LS1mOUTi is at the L level. Wherethe input signal LS1mNi is at the H level (the VDD level), the firstNMOS transistor 112 is ON, the second NMOS transistor 113 is OFF, thefirst PMOS transistor 114 is OFF, and the second PMOS transistor 115 isON, whereby the signal level of the output LS1mOUTi is at the voltagelevel of the signal VGB.

In the present embodiment, a logic-type transistor is used for eachcircuit element preceding the level shift circuit 204, thereby realizinga reduction in the total area. Moreover, the level shift circuit 204itself is made of logic-type transistors, thereby realizing a furtherreduction in the total area.

By using the signal VGB as the high voltage-side power supply of thelevel shift circuit 204 as shown in FIG. 2 so that a voltage of theVDD25 level and a voltage of the VDD level are supplied alternately, itis possible to reduce the stress on the gate oxide films of thetransistors 112 to 115 of the level shift circuit 204, thereby slowingthe progress of the TDDB deterioration.

FIG. 3 shows in detail the level shift circuit 305 in the power supplyswitch circuit 300 of FIG. 1. The level shift circuit 305 includes firstand second NMOS transistors 308 and 309, first and second PMOStransistors 310 and 311, each being a 2.5 V I/O transistor, and aninverter circuit 312 made of 1.2-V logic-type transistors. Thearrangement is similar to that of the level shift circuit 204 describedabove. Note however that the power supply VDD25 is connected to thesource of the first and second PMOS transistors 310 and 311. Theoperation is similar to that of the level shift circuit 204 describedabove.

Thus, by inserting the level shift circuit 305 along the signal linethat is connected to the gate of the PMOS transistor 301 and the CMOStransmission gate 302 of the power supply switch circuit 300, the ON/OFFof the PMOS transistor 301 and the CMOS transmission gate 302 can becontrolled by using the clock signal PCK without having to separatelyprovide an external control terminal. Thus, it is possible to uselogic-type transistors for all circuit elements preceding the levelshift circuit 305, thereby realizing a significant reduction in thetotal area.

FIG. 4 is a waveform diagram showing an operation of the electrical fusecircuit of FIG. 1. The operation of an electrical fuse circuit in whicha plurality of electrical fuse bit cells 200 are connected to the outputsignal terminal of the power supply switch circuit 300 will now bedescribed with reference to FIG. 4.

Referring to FIG. 4, the fuse program enable signal FPEN is fixed to theL level before the start of a programming operation. Therefore, before aprogramming operation, the output INmTi of the second AND circuit 205 ofthe electrical fuse bit cell 200 is fixed to the L level, whereby theNMOS transistor 202 is OFF (disabled). Moreover, the output PRGmIN ofthe NAND circuit 306 of the power supply switch circuit 300 is fixed tothe H level, whereby the PMOS transistor 301 is OFF (disabled) and theoutput VGB of the power supply switch circuit 300 is at the VDD level.

When a programming operation is started, the fuse program enable signalFPEN is transitioned from the L level to the H level which isexemplarily a voltage of 2.5 V, and is input independently of the powersupply VDD25. Then, it is possible to start a programming operation ofthe electrical fuse bit cells 200. Thus, the fuse program enable signalFPEN brings the PMOS transistor 301 and the CMOS transmission gate 302to a programming enabled state at the time of a programming operation.

As described above, a control terminal independent of the power supplyis provided and set to the L level before a programming operation, thusforcibly turning OFF the NMOS transistors 202 of the electrical fuse bitcells 200 and the PMOS transistor 301 of the power supply switch circuit300. Therefore, it is possible to prevent an erroneous breaking of theelectrical fuse element 201 due to an erroneous operation of the levelshift circuits 204 and 305 at the power-on of the power supply, forexample.

While the program clock signal PCK is at the L level, the output LS2mINof the AND circuit 304 of the power supply switch circuit 300 is at theL level (LAPAmTn is initially at the L level), and the output LS2mOUT ofthe level shift circuit 305 is also at the L level. Therefore, theoutput PRGmIN of the NAND circuit 306 is at the H level (the VDD25level), thus turning the PMOS transistor 301 OFF and the CMOStransmission gate 302 ON, whereby the output VGB of the power supplyswitch circuit 300 is at the VDD level (about 1.2 V).

While the program clock signal PCK is at the H level, the output LS2mINof the AND circuit 304 of the power supply switch circuit 300 is at theH level (the VDD level), and the signal LS2mOUT at the H level (theVDD25 level) is output from the level shift circuit 305. With the signalLS2mOUT being at the H level (the VDD25 level) and the signal FPEN beingat the H level (the VDD25 level), the PMOS transistor 301 is turned ON,and the CMOS transmission gate 302 is turned OFF. Therefore, the outputsignal VGB of the power supply switch circuit 300 is at the VDD25 level(about 2.5 V).

Therefore, in synchronism with the clock cycle of the program clocksignal PCK, the signal VGB is at the VDD level while the program clocksignal PCK is at the L level, and is at the VDD25 level while theprogram clock signal PCK is at the H level.

The operation of the electrical fuse circuit will now be described, withrespect to that of the i^(th) stage. When programming the electricalfuse circuit, the program data signal FBmTi is set to the H level whenbreaking the electrical fuse element 201 of the i^(th) stage and set tothe L level when not breaking the electrical fuse element 201 of thei^(th) stage. The electrical fuse bit cell 200 programs the electricalfuse element 201 only when the program enable signal PBmTi is at the Hlevel.

Specifically, the shift register 101 of the programming shift registerblock 100 is controlled by a 1.2-V logic-type power supply VDD, and in acase where the program data signal FBmTi is at the H level (the VDDlevel), a signal at the VDD level is input to the level shift circuit204 while the program enable signal PBmTi is at the H level. The levelshift circuit 204 converts the VDD level to the VDD25 level while thesignal VGB is at the VDD25 level. The output INmTi of the second ANDcircuit 205, receiving the signal LS1mOUTi at the VDD25 level and thefuse program enable signal FPEN at the VDD25 level, goes to the VDD25level (the H level), thereby turning ON the NMOS transistor 202. Then,since the signal VGB is at the VDD25 level, there is a current flowrequired for breaking the electrical fuse element 201, thereby breakingthe electrical fuse element 201.

In a case where the program data signal FBmTi is at the L level, even ifthe program enable signal PBmTi is at the H level, the output LS1mINi ofthe first AND circuit 203 is at the L level, and the output LS1mOUTi ofthe level shift circuit 204 is also at the L level. Therefore, the NMOStransistor 202 is OFF, and there is no current flow through theelectrical fuse element 201, thereby not breaking the electrical fuseelement 201.

The overall operation of the electrical fuse circuit will now bedescribed. The operation of the programming shift register block 100 isas described above with reference to FIGS. 15 to 17, and will not befurther described below.

For example, where the n electrical fuse bit cells 200 are to beprogrammed to 1, 0, . . . , 1, the signal levels of the program datasignal FBmT1, FBmT2, . . . , FBmTn are first set to H, L, . . . , H,respectively.

Then, after the fuse program enable signal FPEN is transitioned to the Hlevel, the program control signal FPGI to be input to the first stage ofthe programming shift register block 100 is raised from the L level tothe H level while keeping a sufficient setup time with respect to therising edge of the program clock signal PCK. The program control signalFPGI at the H level is input to the shift register 101 of the firststage while the program clock signal PCK is at the L level.

The programming shift register block 100 successively produces theprogram enable signals PBmTi (i=1 to n) and the program enabletransmission signals PAmTi (i=1 to n), each having a width equal to onecycle of the program clock signal PCK, as the program clock signal PCKperiodically repeats its cycle.

As the program enable signal PBmTi (i=1 to n) of the electrical fuse bitcell 200 goes to the H level, the electrical fuse bit cell 200 programsthe electrical fuse element 201. Specifically, the states of the signalsLS1mINi (i=1 to n) output from the first AND circuits 203 aresuccessively determined according to the program data signals FBmT1,FBmT2, . . . , FBmTn (=H, L, . . . , H), each at a rising edge of theprogram clock signal PCK.

In the example shown in FIG. 4, the output LS1mINi of the first ANDcircuit 203 of the electrical fuse bit cell 200 of the first stage is atthe H level while the program enable signal PBmT1 of the first stage isat the H level, and the signal LS1mOUT1, which has been converted by thelevel shift circuit 204 to the voltage level of the signal VGB, is inputto the second AND circuit 205, whereby the program signal INmT1 is atthe H level while the program clock signal PCK is at the H level, thusbreaking the electrical fuse element 201 of the first stage.

Even when the program enable signal PBmT2 of the second stage goes tothe H level, the output LS1mIN2 of the first AND circuit 203 of theelectrical fuse bit cell 200 of the second stage stays at the L level,and the signal LS1mOUT2 at the L level and the program signal INmT2 atthe L level are output from the level shift circuit 204 and from thesecond AND circuit 205, respectively, thereby turning OFF the NMOStransistor 202, and thus not breaking the electrical fuse element 201 ofthe second stage. This similarly applies to the third and subsequentstages.

Upon completion of programming of the electrical fuse element 201 of then^(th) stage, the output PAmTn of the programming shift register block100 transitions from the H level to the L level. As the signal LAPAmTnlatched at the H level (the VDD level) is input to the power supplyswitch circuit 300 at this falling edge, the output of the AND circuit304 of the power supply switch circuit 300 transitions to the L level,whereby the output LS2mOUT of the level shift circuit 305 alsotransitions to the L level, irrespective of the program clock signalPCK. Thus, after the completion of a programming operation, theelectrical fuse elements can no longer be programmed.

As described above, with the embodiment of FIG. 1, a plurality ofelectrical fuse elements 201 can be programmed. Moreover, since a highvoltage of VDD25 is not constantly applied to the NMOS transistor 202for passing a current for breaking the electrical fuse element 201, atransistor having a low withstand voltage (e.g., a 1.2-V logic-typetransistor) can be used as the NMOS transistor 202. Thus, 1.2-Vlogic-type transistors can be used as all transistors except for thesecond AND circuit 205 of the electrical fuse bit cell 200, whereby itis possible to significantly reduce the total area as compared with acase where 2.5-V I/O-type transistors are used. Moreover, by using acommon power supply switch circuit 300 for a plurality of electricalfuse bit cells 200, it is possible to reduce the total area of theelectrical fuse circuit.

A cause of an erroneous breaking of the electrical fuse element 201 ofFIG. 1 is an ESD surge current. For example, referring to FIG. 1, if aparasitic diode existing between the P-type silicon substrate of theNMOS transistor 202, which is a program driver for each electrical fusebit cell 200, and the N-type diffusion layer being the drain is turnedON, a surge current flows through the electrical fuse element 201 tothereby erroneously break the electrical fuse element 201. Therefore, inFIG. 1, a diode 400 is inserted between the output signal VGB of thepower supply switch circuit 300 and the ground potential VSS, as acountermeasure against the erroneous breaking of the electrical fuseelement 201 upon ESD application.

Specifically, referring to FIG. 1, the diode 400 is inserted between theoutput signal VGB of the power supply switch circuit 300 and the groundpotential VSS, with the anode of the diode 400 being connected to theground potential VSS, and the cathode thereof being connected to theoutput signal VGB of the power supply switch circuit 300. Upon ESDapplication to the ground potential VSS, the ESD surge current isshunted to the inserted diode 400, thereby preventing the surge currentfrom flowing into the electrical fuse elements 201 of the electricalfuse bit cells 200. Thus, with the provision of the diode 400, it ispossible to prevent the electrical fuse element 201 of each electricalfuse bit cell 200 from being erroneously broken by ESD.

A countermeasure against a surge current upon ESD application to theground potential may be to insert a diode 400 between the groundpotential VSS and the power supply VDD25 and another diode 400 betweenthe ground potential VSS and the power supply VDD. However, as comparedwith a case where two diodes 400 are inserted, one between the groundpotential VSS and the power supply VDD25 and another between the groundpotential VSS and the power supply VDD, it is possible to reduce thenumber of diodes and to reduce the total area of diode inserted as anESD countermeasure with a configuration as shown in FIG. 1 where thediode 400 is inserted between the output signal VGB of the power supplyswitch circuit 300 and the ground potential VSS.

FIG. 5 is a circuit diagram showing a configuration of an electricalfuse circuit according to another embodiment of the present invention.FIG. 6 is a waveform diagram showing an operation of the electrical fusecircuit of FIG. 5.

Similar to the embodiment of FIG. 1, the electrical fuse circuit of theembodiment of FIG. 5 includes a plurality (n) of electrical fuse bitcells 200, a programming shift register block 100 having a plurality (n)of stages, and a power supply switch circuit 300. The components are thesame as those of the embodiment of FIG. 1, except for the power supplyswitch circuit 300.

The power supply switch circuit 300 of the present embodiment will nowbe described. A signal that repeats its cycle in synchronism with theprogram clock signal PCK in a programming operation is used as the fuseprogram enable signal FPEN. Specifically, the input signal is the signalFPEN, which is at the H level (the VDD25 level) while the program clocksignal PCK is at the H level, and at the L level while the program clocksignal PCK is at the L level. The power supply switch circuit 300includes a 2.5-V I/O-type PMOS transistor 308, a 2.5-V I/O-type CMOStransmission gate 309, and 2.5-V I/O-type inverter circuits 310 and 311.Taking the design margin of the power supply VDD into consideration, itis possible to stably pass and output VDD by using the CMOS transmissiongate 309 as transistors that are connected to the power supply VDD.Thus, it is possible to realize a stable output operation of the powersupply switch circuit 300.

With the circuit configuration shown in FIG. 5, the output VGB of thepower supply switch circuit 300 goes to the VDD25 level each time thefuse program enable signal FPEN, which repeats its cycle in synchronismwith the cycle of the program clock signal PCK, rises from the L levelto the H level. Each time the fuse program enable signal FPEN falls fromthe H level to the L level, the output VGB of the power supply switchcircuit 300 goes to the VDD level.

The operation of the electrical fuse bit cell 200 will now be described.The electrical fuse bit cell 200 differs from that of the embodiment ofFIG. 1 only in that the fuse program enable signal FPEN, which is inputto one terminal of a second AND circuit 206, is a signal that repeatsits cycle. In a case where the program data signal FBmTi is at the Hlevel, the output INmTi of the second AND circuit 206 goes to the VDD25level to thereby turn ON the NMOS transistor 202, while the programenable signal PBmTi is at the H level and the signal VGB is at the VDD25level. Then, since the signal VGB is at the VDD25 level, there is acurrent flow required for breaking the electrical fuse element 201,thereby breaking the electrical fuse element 201. In a case where theprogram data signal FBmTi is at the L level, the electrical fuse element201 is not broken.

As described above, the output VGB of the power supply switch circuit300 has the same waveform as that of the embodiment of FIG. 1, and theelectrical fuse bit cell 200 operates as described in the embodiment ofFIG. 1, whereby the overall operation of the electrical fuse circuit issimilar to that of the embodiment of FIG. 1.

Thus, the electrical fuse circuit of the embodiment of FIG. 5 realizes asimilar function to that of the electrical fuse circuit of theembodiment of FIG. 1, with the same input terminal configuration.Moreover, since the PMOS transistor 308 is turned ON/OFF according tothe program enable signal FPEN independent of the power supply, wherebyit is possible to eliminate the need for the level shift circuit 305 andthe preceding control circuits 303 and 304, as compare with theembodiment of FIG. 1, thus realizing a further reduction in the totalarea.

FIG. 7 is a plan view showing an example of a system LSI including theelectrical fuse circuit of FIG. 1 or 5. Illustrated herein is an SoC(System on Chip) including an electrical fuse circuit using two powersupplies of the I/O power supply VDD25 and the power supply VDD, and anelectrical fuse circuit using two power supplies of the I/O power supplyVDD33 and the power supply VDD. The power supply VDD25 (about 2.5 V) issmaller than the power supply VDD33 (about 3.3 V).

Referring to FIG. 7, an I/O cell region extends along the periphery ofthe system LSI, and the system LSI includes the power supply switchcircuit 300, the diode 400 and the electrical fuse section 600(including a plurality of electrical fuse bit cells 200 and theprogramming shift register block 100) arranged in this order from theI/O cell region toward the center of the system LSI. With such anarrangement of the power supply switch circuit 300, the diode 400 andthe electrical fuse section 600, when an ESD surge current is applied tothe VSS terminal in the I/O cell region, the surge current can beabsorbed by the diode 400, which precedes the electrical fuse section600. Thus, it is possible to make effective use of the diode 400, and toprevent electrical fuse elements from being erroneously broken.

In a case where a plurality of I/O power supply voltages (VDD33, VDD25,etc.) are used in a system LSI, circuits using the power supply VDD33may be arranged together (thereby forming what is hereinafter referredto as a “VDD33 power supply island”) and those using the power supplyVDD25 may be arranged together (forming a “VDD25 power supply island”)in the system LSI. If an electrical fuse circuit is compatible only withone I/O power supply, e.g., the power supply VDD25, there will belimitations on the arrangement of the electrical fuse circuit in thesystem LSI. Therefore, it is preferred that an electrical fuse circuitcan be programmed by using different I/O power supplies.

In view of this, transistors manufactured according to the withstandvoltage of the highest I/O power supply voltage among a plurality of I/Opower supplies in the system LSI may be used for all the transistors ofthe PMOS transistor 308, the CMOS transmission gate 309 and the invertercircuits 310 and 311 of the power supply switch circuit 300, in FIG. 5,for example. Specifically, the gate length of all the transistors of thepower supply switch circuit 300 may be set to a length determinedaccording to the withstand voltage of the highest I/O power supplyvoltage among a plurality of I/O power supplies in the system LSI.Moreover, the gate width of the PMOS transistor 308 and the CMOStransmission gate 309 of the power supply switch circuit 300 may be setto a length determined according to the current driving capabilityobtained when using the lowest I/O power supply voltage among aplurality of I/O power supplies in the system LSI. Then, the electricalfuse circuit can be operated by using different I/O power supplyvoltages in the system LSI, whereby it is possible to eliminate thelimitations on the arrangement in the system LSI.

FIG. 8 is a plan view showing another example of a system LSI includingthe electrical fuse circuit of FIG. 1 or 5. The diode 400 is providedaround the electrical fuse section 600 including a plurality ofelectrical fuse bit cells 200. As a result, even if an ESD surge currentis applied to any VSS terminal in the I/O cell region, the surge currentcan be absorbed by the diode 400 even more efficiently, therebypreventing electrical fuse elements from being erroneously broken.

FIG. 9 is a plan view showing a layout of a single I/O cell in thesystem LSI, FIG. 10 is a circuit diagram of FIG. 9, showing a single I/Ocell. FIGS. 9 and 10 show an I/O cell 701, including a VSS line, a VDDline, a VDD25 line as an I/O power supply line for supplying the powersupply from VDD25, a pad 700 for connecting the I/O cell 701 to anexternal terminal, an inverter circuit 702 using VDD25 as its powersupply, and another inverter circuit 703 using VDD as its power supply.The VDD25 power supply line is connected to the electrical fuse circuitby a line IN.

FIG. 11 is a plan view showing still another example of a system LSIincluding the electrical fuse circuit of FIG. 1 or 5, and FIG. 12 is across-sectional view taken along line XII-XII of FIG. 11. In theillustrated example, an electrical fuse circuit including the powersupply switch circuit 300, the diode 400 and the electrical fuse section600 is provided on a system LSI. Referring to FIGS. 11 and 12, each I/Ocell 701 includes the pad 700 connected to an external terminal, the VSSline having the ground potential, the power supply VDD line, and thepower supply VDD25 line. The power supply switch circuit 300, the diode400 and the electrical fuse section 600 are each provided in a layerbelow the pad 700. The power supply switch circuit 300 is electricallyconnected to the power supply VDD25 line via a wiring layer M4. Theprovision of the power supply switch circuit 300, the diode 400 and theelectrical fuse section 600 in a layer below the pad 700 wastes nocircuit area and realizes a reduction in the total area of the systemLSI.

FIG. 13 is a plan view showing still another example of a system LSIincluding the electrical fuse circuit of FIG. 1 or 5, and FIG. 14 is across-sectional view taken along line XIV-XIV of FIG. 13. Also in thisillustrated example, an electrical fuse circuit including the powersupply switch circuit 300, the diode 400 and the electrical fuse section600 is provided on a system LSI. Where the pads 700 are arranged in astaggered pattern as shown in FIGS. 13 and 14, there is produced a spacebelow the pads 700 on the right side (the side closer to the center ofthe system LSI core). The power supply switch circuit 300, the diode 400and the electrical fuse section 600 (including a plurality of electricalfuse bit cells 200 and the programming shift register block 100) areprovided in this layer below the pad 700. The provision of the powersupply switch circuit 300, the diode 400 and the electrical fuse section600 in a layer below the pad 700 wastes no circuit area and realizes areduction in the total area of the system LSI.

As described above, an electrical fuse circuit of the present inventionincludes an independent power supply switch circuit and a plurality ofelectrical fuse bit cells, wherein the electrical fuse bit cells can bemade of LSI logic transistors (e.g., 1.2-V transistors), thus providingan advantage toward a reduction in the total area of the electrical fusecircuit. Moreover, with the provision of a diode between the output ofthe independent power supply switch circuit and the ground potential, itis possible to prevent a surge current from flowing into fuse elementsupon ESD application, whereby it is possible to prevent fuse elementsfrom being erroneously broken and to ensure the safety of an electricalfuse circuit.

An electrical fuse circuit of the present invention is useful inapplications of memory devices with redundancy, secure ID applicationsfor improving the security or protecting copyrights, chip IDapplications for defect analysis of defective chips after assembly, forexample, and analog trimming applications.

1. An electrical fuse circuit, in which a fuse element is broken by acurrent flow therethrough, comprising: an independent power supplyswitch circuit; a fuse element one end of which is connected to anoutput of the power supply switch circuit; and a first MOS transistorconnected to the other end of the fuse element.
 2. The electrical fusecircuit of claim 1, comprising a plurality of fuse bit cells, eachincluding the fuse element and the first MOS transistor.
 3. Theelectrical fuse circuit of claim 1, wherein the power supply switchcircuit includes a first switch transistor and a second switchtransistor, and receives a first power supply voltage and a second powersupply voltage smaller than the first power supply voltage, with one endof the first switch transistor being connected to the first power supplyvoltage, the other end thereof being connected to the output of thepower supply switch circuit, one end of the second switch transistorbeing connected to the second power supply voltage, and the other endthereof being connected to the output of the power supply switchcircuit.
 4. The electrical fuse circuit of claim 3, wherein the firstswitch transistor is a PMOS transistor, and the second switch transistorcomprises a CMOS transmission gate.
 5. The electrical fuse circuit ofclaim 3, wherein the first power supply voltage is an I/O power supplyvoltage of an LSI, and the second power supply voltage is a logic powersupply voltage of the LSI.
 6. The electrical fuse circuit of claim 3,wherein a gate oxide film thickness of the first switch transistor andthe second switch transistor of the power supply switch circuit is equalto that of an I/O circuit of an LSI.
 7. The electrical fuse circuit ofclaim 1, wherein a diode is connected between a ground potential and theoutput of the power supply switch circuit, with an anode of the diodebeing connected to the ground potential and a cathode of the diode beingconnected to the output of the power supply switch circuit.
 8. Theelectrical fuse circuit of claim 7, wherein the power supply switchcircuit, the diode and the plurality of fuse bit cells are arranged inthis order from an I/O power supply cell side of an LSI toward a centerof the LSI.
 9. The electrical fuse circuit of claim 7, wherein diodesare provided around the plurality of fuse bit cells, and the powersupply switch circuit, the diode, the plurality of fuse bit cells andthe diode are arranged in this order from an I/O power supply cell sideof an LSI toward a center of the LSI.
 10. The electrical fuse circuit ofclaim 7, wherein the power supply switch circuit or the diode or some ofthe plurality of fuse bit cells are provided in a layer below a padconnected to an external terminal of an LSI.
 11. The electrical fusecircuit of claim 10, wherein pads connected to external terminals of anLSI are arranged in a staggered pattern, and the power supply switchcircuit or the diode or some of the plurality of fuse bit cells areprovided in a layer below those pads that are located on a side closerto a center of the LSI.
 12. The electrical fuse circuit of claim 2,wherein a gate oxide film thickness of the plurality of fuse bit cellsis equal to that of a logic transistor of an LSI.
 13. The electricalfuse circuit of claim 3, wherein: a plurality of power supply switchcircuits are provided in an LSI; a different first power supply voltageis input to each power supply switch circuit; the first switchtransistors of the plurality of power supply switch circuits all have anequal gate length and an equal gate width; and the second switchtransistors of the plurality of power supply switch circuits all have anequal gate length and an equal gate width.